Add arm64 NEON acceleration#32
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Four chunks/parents per pass in 128-bit vector lanes, generated Go assembly (no cgo) following the upstream C NEON implementation. The generator lives in avo/neon and the committed impl_arm64.s is verified against hash_pure by the same property tests used for AVX2.
Same thresholds as the AVX2 path: HashF for inputs over two chunks, HashP for two or more parents. Below the HashF threshold the 4-lane kernel cannot beat the scalar loop since it always runs 16 blocks.
Bumping the go directive would change loop variable semantics for the existing avx2/sse41 generators; write the neon generator in 1.13-compatible style instead.
Write errors were silently discarded, so an ENOSPC during generation could exit zero and leave truncated assembly behind the redirect.
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On arm64 every input fell back to the pure-Go implementation. This adds a cgo-free NEON backend for chunk and parent hashing, processing four chunks/parents per pass in 128-bit vector lanes, dispatched with the same thresholds as AVX2. The committed
impl_arm64.sis emitted by a small generator inavo/neon(mirroring how the avo-generated amd64 assembly is treated) and is verified againsthash_pureby the same property tests used for AVX2.Apple M4, benchstat n=6:
Unfortunately NEON is fixed at 128 bits by the ARM architecture, so four chunks per pass is the ceiling (versus eight for 256-bit AVX2). ARM's wider SVE extension is optional and not implemented on Apple Silicon yet. Happy to follow up with a PR that interleaves the two independent 4-lane passes into one instruction stream (still single-threaded). That should fill idle NEON slots and boost perf a bit more.