uart_rfifo syntax fix

[RiceShelley]

Fixed small syntax issue in uart block

Syntax error from Vivado. Reminder that slang is used to pickle source files so the line number and filename in the log is not accurate.

| INFO     | blocks_uart_AreaO... | syn_fpga        | 0 | ERROR: [Synth 8-2716] syntax error near '|' [/home/rice/logikbench/examples/sc/build/uart/blocks_uart_AreaOptimized_high/syn_fpga/0/inputs/uart.v:1211]
| INFO     | blocks_uart_AreaO... | syn_fpga        | 0 | INFO: [Synth 8-10285] module 'uart_rfifo' is ignored due to previous errors [/home/rice/logikbench/examples/sc/build/uart/blocks_uart_AreaOptimized_high/syn_fpga/0/inputs/uart.v:1215]
| INFO     | blocks_uart_AreaO... | syn_fpga        | 0 | INFO: [Synth 8-10285] module 'uart_tfifo' is ignored due to previous errors [/home/rice/logikbench/examples/sc/build/uart/blocks_uart_AreaOptimized_high/syn_fpga/0/inputs/uart.v:1632]
| INFO     | blocks_uart_AreaO... | syn_fpga        | 0 | INFO: [Synth 8-10285] module 'uart_transmitter' is ignored due to previous errors [/home/rice/logikbench/examples/sc/build/uart/blocks_uart_AreaOptimized_high/syn_fpga/0/inputs/uart.v:2137]
| INFO     | blocks_uart_AreaO... | syn_fpga        | 0 | INFO: [Synth 8-10285] module 'uart' is ignored due to previous errors [/home/rice/logikbench/examples/sc/build/uart/blocks_uart_AreaOptimized_high/syn_fpga/0/inputs/uart.v:2995]
| INFO     | blocks_uart_AreaO... | syn_fpga        | 0 | INFO: [Synth 8-9084] Verilog file '/home/rice/logikbench/examples/sc/build/uart/blocks_uart_AreaOptimized_high/syn_fpga/0/inputs/uart.v' ignored due to errors
| INFO     | blocks_uart_AreaO... | syn_fpga        | 0 | ERROR: [Synth 8-12188] Failed to read verilog '/home/rice/logikbench/examples/sc/build/uart/blocks_uart_AreaOptimized_high/syn_fpga/0/inputs/uart.v'