This repository contains the implementation of a Combinational Circuit Simulator developed as part of the Testability course project. The project focuses on the fundamental concepts of VLSI testing, specifically implementing logic-level and timing-aware simulations for ISCAS benchmarks.
The simulator is designed to process standard ISCAS-style circuit netlists (.isc) and perform two distinct types of simulation:
- True-Value (Logic) Simulation: A functional simulator to determine the correct output state of the circuit given specific input vectors.
- Event-Driven Gate-Delay Simulation: A more advanced implementation that accounts for propagation delays in logic gates using an event-driven queue, allowing for accurate timing analysis and hazard detection.
- Netlist Parser: Handles reading and mapping ISCAS
.iscfile formats into internal data structures. - Event-Driven Architecture: Efficiently processes signal transitions, minimizing redundant calculations.
- Support for Benchmarks: Tested and validated with standard circuits like
newbyte.iscandt.isc. - Waveform Analysis: Supports custom test patterns for verification.
.
├── True_sim.py # Core logic simulation script
├── Delay_sim.py # Event-driven delay simulation script
├── newbyte.isc # Benchmark circuit file
├── t.isc # Benchmark circuit file
├── wave-form/ # Directory containing input test vectors
│ ├── 1.txt
│ └── 2.txt
└── .gitignore # Git ignore configuration
This repository contains Phase 1 of the Testability course project, focused on combinational circuit simulation.
For the continuation of this work on fault simulation and fault coverage analysis, see:
- Phase 2 — ISC Fault Simulator:
isc-fault-simulator
Phase 2 extends the simulation framework developed in this repository to support stuck-at fault modeling, serial fault simulation, and fault coverage evaluation.