TEMP: exercise gf180mcu DRC + LVS layermap fix#7
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Exercises the gf180mcu LVS layermap fix and the drc_klayout plugin end-to-end in cloud build, using PR #323's merged backend. Do NOT merge — revert before any merge to main.
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Do NOT merge. Temporary PR to drive a cloud build with:
ihp_sg13g2+block→gf180mcu+pga144[chipflow.backend.check.drc] enable = trueso drc_klayout actually runsGoal: verify chipflow-backend PR #323 (gf180mcu edi2gds layermap install + drc_klayout / lvs_klayout gating refactor) end-to-end on a real cloud build.
What this exercises:
klayout:lvsproduces "extracted netlist fully match output verilog file"klayout:drc:gf180mcuandklayout:drc:gf180mcu_antennacomplete and ship.lyrdbreportsRevert before merging — this PR is for triggering CI only.