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TEMP: exercise gf180mcu DRC + LVS layermap fix #7

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TEMP: exercise gf180mcu DRC + LVS layermap fix #7

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13 changes: 8 additions & 5 deletions upcounter/chipflow.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -10,13 +10,16 @@ default = 'sys_clk'
[chipflow.resets]
default = 'sys_rst_n'

# TEMP: switched from ihp_sg13g2/block to gf180mcu/pga144 to exercise
# the gf180mcu LVS layermap fix + drc_klayout plugin end-to-end in the
# cloud build. Revert this file before merging.
[chipflow.silicon]
process = "ihp_sg13g2"
package = "block"
process = "gf180mcu"
package = "pga144"

[chipflow.silicon.block]
width = 5
height = 5
# TEMP: enable the manifest DRC gate so drc_klayout actually runs.
[chipflow.backend.check.drc]
enable = true

[chipflow.silicon.pads]
# System (no fixed locations for blocks — auto-allocated)
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