[Power] Refine power estimation flow and add power evaluation flow

[qianxu1998]

Summary

• Move and expand the estimate-power flow into tools/dynamatic/power, add Verilog support, stage selection (pre/post), and optional post-synthesis netlist generation for higher-accuracy SAIF generation.
• Add a new evaluate-power flow (frontend command + Python + TCL template) that builds and optionally runs a Vivado XSim-based power evaluation script; supports synth/impl stages and optional hierarchy flattening. For now this is Verilog-only, and produces both functional and timing power reports per stage.
• Plumb the configured clock period into the simulation/testbench path so timing simulation and SAIF generation use the correct clock period.

Script details

• tools/dynamatic/power/estimate_power.py
  • Args: --output_dir, --kernel_name, --hdl (vhdl|verilog), --synth (pre|post), --cp, --vivado_cmd
  • Behavior: generates period.xdc, Modelsim .do, optional pre-synth via Vivado, then report_power.tcl using SAIF from simulation.
• tools/dynamatic/power/power_eval.py
  • Args: --output_dir, --kernel_name, --hdl (verilog|verilog-beta|vhdl), --stage (synth|impl), --flatten_hierarchy, --cp, --vivado_cmd, --no-run
  • Behavior: emits power_extraction.tcl to run XSim, dump SAIF/VCD, and generate power reports; runs Vivado unless --no-run is set.

Usage (Dynamatic Frontend)

# estimate-power
estimate-power --hdl verilog --synth pre

# evaluate-power (Verilog backend only)
evaluate-power --hdl verilog --stage impl --flatten-hierarchy 1

[murphe67]

in-memory? comment outdated, or something I don't understand?

[murphe67]

should we throw an error if the xdc file doesnt exist? the dict structure enforces that we pass an xdc file right? so if we have a typo in the name, should we tell the user?

[murphe67]

dumb q from me: set_property applies separately to sources_1 and sim_1? we are not overriding the previous set_top from line 43?

maybe a comment would help for someone learning about power estimation from this script

[murphe67]

maybe a comment about what the vhdl files we want are when hdl is verilog?

[murphe67]

mild recommendation:

if hdl == "verilog":
elseif hdl == "vhdl":
else
throw error

had a lot of bugs in my code from stuff like this from python

[murphe67]

same mild recc here of error on unrecognized hdl

[murphe67]

add print or throw error? seem risky to do quietly