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b9d1973
[Power] Add support for Verilog backend for power estimation flow
qianxu1998 Jan 19, 2026
d6c42d4
Merge remote-tracking branch 'origin/main' into power_analysis
qianxu1998 Jan 19, 2026
72208dc
[Power] Change the name of the top folder containing power_estimate s…
qianxu1998 Jan 19, 2026
3e93de0
[Power] Update flags for estimate-power
qianxu1998 Jan 19, 2026
1f271b8
[Sim] Make simpackage.vhd and single_argument.vhd compatible and runn…
qianxu1998 Jan 19, 2026
9e54d30
Merge remote-tracking branch 'origin/main' into power_analysis
qianxu1998 Jan 25, 2026
c2fc69e
[HLS-verf] pass clock period ot hls-verifier to change the HALF_CLOCK…
qianxu1998 Jan 25, 2026
05e17c6
Initial commit for the power_evaluation tcl generation script
qianxu1998 Jan 27, 2026
4bb0548
Add clock period variable in simulate.sh
qianxu1998 Jan 27, 2026
d1528a0
Fix bug in the added evaluate-power flag
qianxu1998 Jan 27, 2026
039b3c2
Merge remote-tracking branch 'origin/main' into power_analysis
qianxu1998 Jan 27, 2026
865e671
Change the default vivado command in estimate_power.py script
qianxu1998 Jan 27, 2026
02b4534
Finalize power_extraction.tcl generation script
qianxu1998 Jan 27, 2026
5297cfa
Merge remote-tracking branch 'origin/main' into power_analysis
qianxu1998 Jan 30, 2026
74f3672
Fix the problem during testbench generation
qianxu1998 Jan 30, 2026
058b9eb
Merge remote-tracking branch 'origin/main' into power_analysis
qianxu1998 Jan 30, 2026
006e79a
Fix bug when generating clock period in the testbench
qianxu1998 Jan 30, 2026
9af7d7c
Ensure verilog simulation will not exit early in Modelsim
qianxu1998 Jan 30, 2026
c763b8b
Update estimate_power script for the new hls_verifier
qianxu1998 Jan 30, 2026
dc1003b
remove redudant hdl parameter parsing
qianxu1998 Jan 30, 2026
5cf95f9
Adapt script to generate power extraction script
qianxu1998 Jan 31, 2026
b0530da
Merge remote-tracking branch 'origin/main' into power_analysis
qianxu1998 Jan 31, 2026
03f7617
Early exit when hdl is VHDL for power analysis
qianxu1998 Jan 31, 2026
8380249
Merge branch 'main' into power_analysis
qianxu1998 Feb 7, 2026
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107 changes: 104 additions & 3 deletions tools/dynamatic/dynamatic.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -380,11 +380,48 @@ class Synthesize : public Command {

class EstimatePower : public Command {
public:
static constexpr llvm::StringLiteral HDL = "hdl";
static constexpr llvm::StringLiteral STAGE = "stage";

EstimatePower(FrontendState &state)
: Command("estimate-power",
"Estimate the power consumption of the design using switching "
"activity from simulation.",
state) {}
state) {
addOption({HDL, "HDL type, vhdl or verilog"});
addOption({STAGE,
"The netlist used for functional simulation (pre or post "
"synthesis) in Modelsim to generate SAIF file, options are "
"'pre' and 'post' (default : 'pre')"});
}

CommandResult execute(CommandArguments &args) override;
};

class PowerEval : public Command {
public:
static constexpr llvm::StringLiteral HDL = "hdl";
static constexpr llvm::StringLiteral STAGE = "stage";
static constexpr llvm::StringLiteral FLATTEN_HIERARCHY = "flatten-hierarchy";

PowerEval(FrontendState &state)
: Command(
"evaluate-power",
"Runs the Vivado flow and vector-based power evaluation at "
"different design stages,"
"using switching activity from simulation based on XSIM in Vivado.",
state) {
addOption({HDL, "HDL type, vhdl or verilog"});
addOption({STAGE,
"Stage (synth or impl) to perform simulation with xsim and "
"vector-based power "
"evaluation, synthesis or implementation, default : synth"});
addOption(
{FLATTEN_HIERARCHY,
"Control hierarchy flattening during synthesis. If set, the "
"fully flattened flow is used. If not set, the FLATTEN_HIERARCHY "
"none property is emitted."});
}

CommandResult execute(CommandArguments &args) override;
};
Expand Down Expand Up @@ -808,7 +845,7 @@ CommandResult Simulate::execute(CommandArguments &args) {
return execCmd(script, state.dynamaticPath, state.getKernelDir(),
state.getOutputDir(), state.getKernelName(), state.vivadoPath,
state.fpUnitsGenerator == "vivado" ? "true" : "false",
simulator, state.hdl);
simulator, floatToString(state.targetCP, 2), state.hdl);
}

CommandResult Visualize::execute(CommandArguments &args) {
Expand Down Expand Up @@ -845,14 +882,77 @@ CommandResult EstimatePower::execute(CommandArguments &args) {
if (!state.sourcePathIsSet(keyword))
return CommandResult::FAIL;

// Get simulation stage configuration
std::string stage = "pre";

if (auto it = args.options.find(STAGE); it != args.options.end()) {
if (it->second == "pre" || it->second == "post") {
stage = it->second;
} else {
llvm::errs() << "Unknow stage '" << it->second
<< "', possible options are 'pre' and 'post'.\n";
return CommandResult::FAIL;
}
}

std::string script =
state.dynamaticPath + "/tools/dynamatic/power/estimate_power.py";

// clang-format off
return execCmd(
"python", script,
"--output_dir", state.getOutputDir(),
"--kernel_name", state.getKernelName(),
"--hdl", state.hdl,
"--synth", stage,
"--cp", floatToString(state.targetCP, 3)
);
// clang-format on
}

CommandResult PowerEval::execute(CommandArguments &args) {
// We need the source path to be set
if (!state.sourcePathIsSet(keyword))
return CommandResult::FAIL;

// Get simulation stage configuration
std::string stage = "synth";

if (auto it = args.options.find(STAGE); it != args.options.end()) {
if (it->second == "synth" || it->second == "impl") {
stage = it->second;
} else {
llvm::errs() << "Unknow stage '" << it->second
<< "', possible options are 'synth' and 'impl'.\n";
return CommandResult::FAIL;
}
}

// Get flatten hierarchy configuration
std::string flattenHierarchy = "1";

if (auto it = args.options.find(FLATTEN_HIERARCHY);
it != args.options.end()) {
if (it->second == "0" || it->second == "1") {
flattenHierarchy = it->second;
} else {
llvm::errs() << "Unknow flatten hierarchy option '" << it->second
<< "', possible options are '0' (not set) and '1' (set).\n";
return CommandResult::FAIL;
}
}

std::string script =
state.dynamaticPath + "/tools/dynamatic/estimate_power/estimate_power.py";
state.dynamaticPath + "/tools/dynamatic/power/power_eval.py";

// clang-format off
return execCmd(
"python", script,
"--output_dir", state.getOutputDir(),
"--kernel_name", state.getKernelName(),
"--hdl", state.hdl,
"--stage", stage,
(flattenHierarchy == "1" ? "--flatten_hierarchy" : ""),
"--cp", floatToString(state.targetCP, 3)
);
// clang-format on
Expand Down Expand Up @@ -931,6 +1031,7 @@ int main(int argc, char **argv) {
commands.add<Visualize>(state);
commands.add<Synthesize>(state);
commands.add<EstimatePower>(state);
commands.add<PowerEval>(state);
commands.add<Help>(state);
commands.add<Exit>(state);

Expand Down
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