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Add bp_processor (Black-Parrot quad-core, e_bp_multicore_4_cfg) as a new HighTide benchmark design. RTL is generated from SystemVerilog via sv2v, with large SRAM memories (>= 1024 bits) mapped to FakeRAM macros to keep ABC synthesis tractable (~304K gates, 140 SRAM macros, 7.5 min synth). - setup.sh: sv2v conversion from Black-Parrot repo flist.vcs, followed by patch_mem.py (strips bsg_mem_*_synth register arrays) and gen_fakeram.py (generates FakeRAM LEF/LIB and parameterized macros.v replacements) - 8 FakeRAM configs for ASAP7 (512x64, 512x8, 128x8, 64x184, 64x50, 32x66, 32x48, 8x174) - Hierarchical synthesis with SYNTH_MINIMUM_KEEP_SIZE=500 - 1500ps clock period, 800x800 die area
Restructure to match the liteeth convention where the design family is the parent directory and specific configurations are subdirectories.
Macros were consuming 50% of core area at 800x800 (56% utilization). New 1020x1020 die gives ~34% utilization for macro halos and routing. Added PLACE_PINS_ARGS to spread IO pins on perimeter.
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Initial bp_quad design working.