Black parrot

.gitmodules

@@ -19,3 +19,6 @@
 [submodule "designs/src/gemmini/dev/repo"]
 	path = designs/src/gemmini/dev/repo
 	url = https://github.com/ucb-bar/gemmini.git
+[submodule "designs/src/bp_processor/dev/repo"]
+	path = designs/src/bp_processor/dev/repo
+	url = https://github.com/black-parrot/black-parrot.git

Makefile

@@ -11,6 +11,7 @@
 # DESIGN_CONFIG=./designs/asap7/lfsr_prbs_gen/config.mk
 # DESIGN_CONFIG=./designs/asap7/NyuziProcessor/config.mk
 # DESIGN_CONFIG=./designs/asap7/gemmini/config.mk
+# DESIGN_CONFIG=./designs/asap7/bp_processor/bp_quad/config.mk
 
 DESIGN_CONFIG ?= ./designs/nangate45/lfsr_prbs_gen/config.mk
 -include OpenROAD-flow-scripts/flow/Makefile

designs/asap7/bp_processor/bp_quad/config.mk

@@ -0,0 +1,43 @@
+export DESIGN_NICKNAME ?= bp_quad
+export DESIGN_NAME = bp_processor
+export PLATFORM    = asap7
+
+export DEV_DESIGN_HOME = $(DESIGN_NAME)/dev
+
+export SYNTH_HIERARCHICAL = 1
+export SYNTH_MINIMUM_KEEP_SIZE = 500
+
+-include $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/verilog.mk
+
+export ABC_AREA = 1
+
+export SDC_FILE      = $(PLATFORM_DESIGN_DIR)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export ADDITIONAL_LEFS = $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_8x174_1rw.lef \
+                         $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_32x48_1rw.lef \
+                         $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_32x66_1rw.lef \
+                         $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_64x50_1rw.lef \
+                         $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_64x184_1rw.lef \
+                         $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_128x8_1rw.lef \
+                         $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_512x8_1rw.lef \
+                         $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_512x64_1rw.lef
+
+export ADDITIONAL_LIBS = $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_8x174_1rw.lib \
+                         $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_32x48_1rw.lib \
+                         $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_32x66_1rw.lib \
+                         $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_64x50_1rw.lib \
+                         $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_64x184_1rw.lib \
+                         $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_128x8_1rw.lib \
+                         $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_512x8_1rw.lib \
+                         $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_512x64_1rw.lib
+
+export SYNTH_MEMORY_MAX_BITS = 65536
+
+export DIE_AREA  = 0 0 1020 1020
+export CORE_AREA = 10 10 1010 1010
+
+export PLACE_PINS_ARGS = -min_distance 30 -min_distance_in_tracks
+export MACRO_PLACE_HALO    = 6 6
+export MACRO_BLOCKAGE_HALO = 0.5
+export PLACE_DENSITY_LB_ADDON = 0.10
+export TNS_END_PERCENT     = 100

designs/asap7/bp_processor/bp_quad/constraint.sdc

@@ -0,0 +1,18 @@
+current_design bp_processor
+
+set clk_name  CLK
+set clk_port_name clk_i
+set clk_period 3333
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+
+set_driving_cell -lib_cell DFFHQNx2_ASAP7_75t_R -pin QN $non_clock_inputs
+set_load [expr 4.0 * 0.683716] [all_outputs]

designs/asap7/bp_processor/bp_quad/io.tcl

@@ -0,0 +1,89 @@
+# IO Pin Constraints for bp_quad (bp_processor) on ASAP7
+#
+# Pin distribution across 4 sides:
+#   BOTTOM (269 pins): Control signals + DMA data inputs
+#   TOP    (340 pins): DMA data outputs + DMA packet outputs
+#   LEFT   (390 pins): Memory Forward interface (in + out)
+#   RIGHT  (390 pins): Memory Reverse interface (in + out)
+#
+# Each bus is a separate -group to keep bits ordered together.
+# min_distance 40 tracks (1.92um) in PLACE_PINS_ARGS spreads
+# pins across <75% of each side.
+
+# Helper: generate bus pin names in order
+proc bus_pins {name high {low 0}} {
+    set pins {}
+    for {set i $low} {$i <= $high} {incr i} {
+        lappend pins "${name}\[${i}\]"
+    }
+    return $pins
+}
+
+# ============================================================
+# BOTTOM: Control + DMA data inputs
+# ============================================================
+# Side assignment for all bottom pins
+set_io_pin_constraint -region bottom:* -pin_names [list \
+    clk_i rt_clk_i reset_i \
+    {*}[bus_pins my_did_i 2] \
+    {*}[bus_pins host_did_i 2] \
+    {*}[bus_pins dma_data_v_i 1] \
+    {*}[bus_pins dma_data_ready_and_o 1] \
+    {*}[bus_pins dma_data_i 255] \
+]
+# Group each bus so bits stay ordered together
+set_io_pin_constraint -group -order -pin_names [bus_pins my_did_i 2]
+set_io_pin_constraint -group -order -pin_names [bus_pins host_did_i 2]
+set_io_pin_constraint -group -order -pin_names [bus_pins dma_data_v_i 1]
+set_io_pin_constraint -group -order -pin_names [bus_pins dma_data_ready_and_o 1]
+set_io_pin_constraint -group -order -pin_names [bus_pins dma_data_i 255]
+
+# ============================================================
+# TOP: DMA data outputs + DMA packet outputs
+# ============================================================
+set_io_pin_constraint -region top:* -pin_names [list \
+    {*}[bus_pins dma_data_o 255] \
+    {*}[bus_pins dma_data_v_o 1] \
+    {*}[bus_pins dma_data_ready_and_i 1] \
+    {*}[bus_pins dma_pkt_o 75] \
+    {*}[bus_pins dma_pkt_v_o 1] \
+    {*}[bus_pins dma_pkt_ready_and_i 1] \
+]
+set_io_pin_constraint -group -order -pin_names [bus_pins dma_data_o 255]
+set_io_pin_constraint -group -order -pin_names [bus_pins dma_data_v_o 1]
+set_io_pin_constraint -group -order -pin_names [bus_pins dma_data_ready_and_i 1]
+set_io_pin_constraint -group -order -pin_names [bus_pins dma_pkt_o 75]
+set_io_pin_constraint -group -order -pin_names [bus_pins dma_pkt_v_o 1]
+set_io_pin_constraint -group -order -pin_names [bus_pins dma_pkt_ready_and_i 1]
+
+# ============================================================
+# LEFT: Memory Forward interface
+# ============================================================
+set_io_pin_constraint -region left:* -pin_names [list \
+    mem_fwd_v_i mem_fwd_ready_and_o \
+    {*}[bus_pins mem_fwd_header_i 64] \
+    {*}[bus_pins mem_fwd_data_i 127] \
+    mem_fwd_v_o mem_fwd_ready_and_i \
+    {*}[bus_pins mem_fwd_header_o 64] \
+    {*}[bus_pins mem_fwd_data_o 127] \
+]
+set_io_pin_constraint -group -order -pin_names [bus_pins mem_fwd_header_i 64]
+set_io_pin_constraint -group -order -pin_names [bus_pins mem_fwd_data_i 127]
+set_io_pin_constraint -group -order -pin_names [bus_pins mem_fwd_header_o 64]
+set_io_pin_constraint -group -order -pin_names [bus_pins mem_fwd_data_o 127]
+
+# ============================================================
+# RIGHT: Memory Reverse interface
+# ============================================================
+set_io_pin_constraint -region right:* -pin_names [list \
+    mem_rev_v_i mem_rev_ready_and_o \
+    {*}[bus_pins mem_rev_header_i 64] \
+    {*}[bus_pins mem_rev_data_i 127] \
+    mem_rev_v_o mem_rev_ready_and_i \
+    {*}[bus_pins mem_rev_header_o 64] \
+    {*}[bus_pins mem_rev_data_o 127] \
+]
+set_io_pin_constraint -group -order -pin_names [bus_pins mem_rev_header_i 64]
+set_io_pin_constraint -group -order -pin_names [bus_pins mem_rev_data_i 127]
+set_io_pin_constraint -group -order -pin_names [bus_pins mem_rev_header_o 64]
+set_io_pin_constraint -group -order -pin_names [bus_pins mem_rev_data_o 127]