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arch/mips/jz4780: Add support for L2 cache operations#19494

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xiaoxiang781216 merged 1 commit into
apache:masterfrom
ldube:ci20
Jul 21, 2026
Merged

arch/mips/jz4780: Add support for L2 cache operations#19494
xiaoxiang781216 merged 1 commit into
apache:masterfrom
ldube:ci20

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@ldube

@ldube ldube commented Jul 21, 2026

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Summary

The common mips_cache.S only handles generic L1 cache operations and does not support L2 (secondary) cache operations required for the JZ4780 target.

This commit introduces mti_cache.S to support both L1 and L2 cache operations.

The mti_cache.S implementation is BSD licensed from Imagination Technologies.

Impact

Only CI20.

Testing

Tested "net" configuration on MIPS CI20

$ telnet 192.168.2.3
Trying 192.168.2.3...
Connected to 192.168.2.3.
Escape character is '^]'.

NuttShell (NSH) NuttX-13.0.0
nsh> uname -a
NuttX 13.0.0 8c115a1 Jul 20 2026 22:49:32 mips ci20
nsh>

@ldube
ldube requested review from Ouss4 and liuguo09 as code owners July 21, 2026 02:53
@github-actions github-actions Bot added Arch: mips Issues related to the MIPS architecture Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. Board: mips labels Jul 21, 2026
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github-actions Bot commented Jul 21, 2026

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MemBrowse Memory Report

No memory changes detected for:

The common mips_cache.S only handles generic L1 cache operations and
does not support L2 (secondary) cache operations required for the
JZ4780 target.

This commit introduces mti_cache.S to support both L1 and L2 cache
operations.

The mti_cache.S implementation is BSD licensed from Imagination
Technologies.

Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
@xiaoxiang781216
xiaoxiang781216 merged commit 784035a into apache:master Jul 21, 2026
53 checks passed
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Arch: mips Issues related to the MIPS architecture Board: mips Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces.

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3 participants