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arch/mips/jz4780: Add support for L2 cache operations #19494

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Merged
xiaoxiang781216 merged 1 commit into from
Jul 21, 2026
Merged

arch/mips/jz4780: Add support for L2 cache operations #19494

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4 changes: 2 additions & 2 deletions arch/mips/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -34,12 +34,12 @@ config ARCH_CHIP_JZ4780
bool "JZ4780"
select ARCH_MIPS32
select ARCH_MIPS_XBURST1
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_IRQPRIO
select ARCH_VECNOTIRQ
select ARCH_HAVE_RESET
select ARCH_HAVE_SERIAL_TERMIOS
select MIPS32_HAVE_DCACHE
select MIPS32_HAVE_ICACHE
select MIPS32_USE_WAIT_INSTRUCTION
select MIPS32_USE_SYSCALL_INSTRUCTION
---help---
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8 changes: 6 additions & 2 deletions arch/mips/src/jz4780/Make.defs
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Expand Up @@ -26,7 +26,7 @@ HEAD_ASRC = jz4780_head.S

# Common MIPS files

CMN_ASRCS = mips_syscall0.S fork.S mips_cache.S
CMN_ASRCS = mips_syscall0.S fork.S
CMN_CSRCS += mips_allocateheap.c mips_copystate.c mips_createstack.c
CMN_CSRCS += mips_doirq.c mips_exit.c mips_getintstack.c mips_initialize.c
CMN_CSRCS += mips_initialstate.c mips_irq.c mips_lowputs.c
Expand All @@ -44,6 +44,10 @@ endif

# Required JZ4780 files

CHIP_ASRCS =
ifeq ($(CONFIG_ALLOW_BSD_COMPONENTS),y)
CHIP_ASRCS = mti_cache.S
endif

CHIP_CSRCS = jz4780_lowinit.c jz4780_exception.c jz4780_decodeirq.c
CHIP_CSRCS += jz4780_irq.c jz4780_timerisr.c jz4780_gpio.c
CHIP_CSRCS += jz4780_cache.c
2 changes: 2 additions & 0 deletions arch/mips/src/jz4780/chip.h
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Expand Up @@ -34,6 +34,8 @@
* Pre-processor Definitions
****************************************************************************/

#define JZ4780_DCACHE_LINESIZE 32

/****************************************************************************
* Public Types
****************************************************************************/
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