fix(cosim): CS-gate QSPI MISO injection for shared-bus arbitration#183
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Plural QSPI memories may share one SCK/SIO bus selected by distinct CS lines (same clk_gpio/d0_gpio, distinct csn_gpio). That never worked: gpu_apply_flash_din (and the CpuBackend mirror) wrote every instance's d_i to its d_in_pos unconditionally, so a deselected flash — which holds its last d_i and is often iterated last — clobbered the selected driver's MISO. Last-writer-wins silently corrupted the shared-bus reads. Gate the injection on selection: a deselected instance (prev_csn high) presents high-Z and does not drive. Fix mirrored across all backends — CpuBackend::apply_flash_din_gated (extracted as a pure, unit-testable fn) and the gpu_apply_flash_din kernels (Metal + the shared CUDA/HIP kernel_v1_impl.cuh). Gating on prev_csn (the delayed csn that produced d_i) keeps the driven value and the selection decision in phase with the setup-delay model. Independent-pin plurality (multi_mem_cosim) is unaffected — a deselected flash on its own pins was always ignored. Tests: - flash_din_tests unit tests: selected drives, deselected is high-Z, shared-bus order-independence, xmask clear-only-when-driven. - tests/qspi_shared_bus/: RTL fixture — two flashes on a shared bus, distinct CS; reads 0xA1 / 0xB2. Golden (CpuBackend, byte-identical to Metal/CUDA/HIP) + content check, wired into the all/qspi CI scopes. Verified it FAILS without the gate (fa reads 0xFF, clobbered). Also corrects a stale `len() <= 1` doc comment (real cap is MAX_QSPI_MEMS = 4) and amends ADR 0013. Co-developed-by: Claude Code v2.1.203 (claude-opus-4-8[1m])
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robtaylor
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Jul 9, 2026
Rename derived-clock-185 → c64-cosim-blockers. The next Jacquard session's two next steps are #185 (derived clock, in progress on this branch) and #186 (SRAM macro panic, flatten.rs:1268, unstarted), plus context: #183 merged, #184 video tap ready. Cross-session coordination stays on the GitHub issues, not in a handoff. Co-developed-by: Claude Code v2.1.203 (claude-opus-4-8[1m])
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Problem
Plural QSPI memories can be configured on a shared SCK/SIO bus with distinct CS lines (same
clk_gpio/d0_gpio, distinctcsn_gpio) — but it never worked.gpu_apply_flash_din(and the CpuBackend mirror) wrote every instance'sd_ito itsd_in_posunconditionally, regardless of CS. A deselected flash holds its lastd_i(idle0x0F) and, being iterated last, overwrote the selected flash's MISO on the shared line — last-writer-wins, silently corrupting reads.Independent-pin plurality (
tests/multi_mem_cosim) was fine; only the shared-bus topology was affected.Fix
CS-gate the MISO injection: a deselected instance (
prev_csnhigh) presents high-Z and does not drive. Mirrored across all backends:CpuBackend::apply_flash_din_gated— extracted as a pure, GPU/netlist-free, unit-testable fn.gpu_apply_flash_din— Metal (kernel_v1.metal) + the shared CUDA/HIPkernel_v1_impl.cuh.Gating on
prev_csn(the delayed CS that producedd_i) keeps the driven value and the selection decision in phase with the existing setup-delay model.Tests
flash_din_tests): selected drives its lane; deselected is high-Z; shared-bus arbitration is order-independent; xmask cleared only when driven.tests/qspi_shared_bus/): one master, two flashes on a shared bus with distinct CS, reads0xA1/0xB2. Byte-exact golden (CpuBackend, verified byte-identical to Metal) +check.pycontent assertion, wired into theall+qspiscopes ofcosim_cpu_check.sh(gates CpuBackend/Linux + the CUDA/HIP/Metal GPU suites).fareads0xFF, clobbered) — the test catches the bug.Locally: full
allcosim scope passes (12 fixtures, no regressions) on both CpuBackend and Metal;--check-with-cpushows 0 output/SRAM mismatches (the input-state noise is pre-existing, identical on untouchedmulti_mem).Also
len() <= 1doc comment (real cap isMAX_QSPI_MEMS = 4).