Projeto e síntese lógica de uma Unidade Lógica e Aritmética (ULA) parametrizável em SystemVerilog utilizando Synopsys Design Compiler (Tecnologia SAED32).
-
Updated
Jul 22, 2026 - Verilog
#
design-compiler
Here are 6 public repositories matching this topic...
Projeto introdutório de síntese lógica de uma porta AND em SystemVerilog utilizando o Synopsys Design Compiler com a biblioteca SAED32.
-
Updated
Jul 22, 2026 - Tcl
🎯 AI PPT Design Compiler — 从用户需求到可编辑 PowerPoint 的本地化演示文稿设计引擎。模块化页面渲染器、结构化 Schema、Design Planner、PPTX 输出。
-
Updated
Jul 25, 2026 - Python
The RISCV project was converted from RTL code to GDS II format using 14nm PDKs. This was implemented with the ICC2 and Design Compiler NXT EDA tools from Synopsys, following a Flat Design Style
-
Updated
Jun 3, 2025 - Verilog
Functional Verification, ASIC Synthesis and Formal Verification of an AMBA Memory Interface Bridge integrated with the LEON3 Processor and GRETH Ethernet MAC.
asic software-testing formal-verification leda amba-apb design-compiler amba-ahb standalone-testing bridge-module
-
Updated
Jun 28, 2026 - C
An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.
asic rtl verilog synthesis hdl vlsi digital-design demux icc2 floorplanning hardware-design clock-tree-synthesis rtl-to-gdsii design-compiler
-
Updated
Jun 4, 2025
Improve this page
Add a description, image, and links to the design-compiler topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the design-compiler topic, visit your repo's landing page and select "manage topics."