Single Event Upset simulator built on TurnaCore
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Updated
Oct 10, 2023 - Python
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single-event-upset
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Transistor-level LTspice study of a standard 6T SRAM cell, Single Event Upset fault injection, and a radiation-hardened DICE memory cell for space electronics applications.
sram seu cmos ic-design analog-ic-design ltspice memory-cells single-event-upset radiation-effects radiation-hardened dice-latch space-electronics semiconductor-reliability
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Updated
May 29, 2026
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