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Pull requests: xupgit/Basys3
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Make reset polarity consistent with the verilog implementation
#4
opened Apr 25, 2017 by
DmytroLevit
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Basys3/Projects/Logic_Design/SN_Design/digital_clock/src/digital_clock.tcl
#3
opened Jun 15, 2016 by
artalex97
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