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Basys3/Projects/Logic_Design/SN_Design/digital_clock/src/digital_clock.tcl#3

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artalex97 wants to merge 42 commits intowwfrom
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Basys3/Projects/Logic_Design/SN_Design/digital_clock/src/digital_clock.tcl#3
artalex97 wants to merge 42 commits intowwfrom
master

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xupgit and others added 12 commits June 23, 2015 08:37
Updated readme
Quickstart guide
Added YouTube
Embedded YouTube video
Updated typo
First version, WS2812 LED IP
Update Readme
Update readme
Fixed Digilent link for Basys3
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3 participants