Basys3/Projects/Logic_Design/SN_Design/digital_clock/src/digital_clock.tcl

Library/Interface/7-Segments-Display/seg7display_1.0/doc/readme.txt

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+Tool and version:  Vivado 2014.4 
+Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq
+
+Introduction:
+This interface IP displays either a 16-bit or 32-bit input, consists of either 4 or 8 nibbles data, on either one or two modules having 4 7-segments displays each. It expects either 16-bit or 32-bit input data, typically driven through GPIO port, 100 MHz clock input, and high-level reset signal. It outputs either 4 or 8 anode controls at approximately 50 Hz. The decimal point on the display is turned ON or OFF based on the configurable parameter of individual segment's decimal point. The section is based on configurable parameter MODULES. If MODULES=0 then it expects 16-bit input and will output 4 anode and time-multiplexed one decimal point signals, otherwise it expects 32-bit input and will output 8 anode and time-multiplexed two decimal point signals.
+
+Input/Output Ports:
+Input:
+clk - 100 MHz clock
+reset - high-level logic
+x_l - 16-bit input composed of four nibbles. Bits [3:0] is the least significant whose value is displayed on the right-most module. Bits [31:28] is the most significant whose value is displayed on the left-most segment of the right side module.
+x_h - 16-bit input composed of four nibbles. Bits [3:0] is the least significant whose value is displayed on the right-most module. Bits [31:28] is the most significant whose value is displayed on the left-most segment of the left side module.
+
+Output:
+a_to_g - 7-bit output controlling 7 segments. The least-significant bit controls segment "a" where as the most-significant bit controls segment "g".
+an_l - 4-bit output controlling enabling of four anodes of the right-most module at roughly 50 Hz rate.The least-significant bit controls right-most segment where as the most-significant bit controls left-most segment. 
+an_h - 4-bit output controlling enabling of four anodes of the left-most module at roughly 50 Hz rate.The least-significant bit controls right-most segment where as the most-significant bit controls left-most segment. 
+dp_l - controls whether the corresponding decimal point to be turned ON or not. This will be to control right-most module
+dp_h - controls whether the corresponding decimal point to be turned ON or not. This will be to control left-most module
+
+Setting up the library path:
+Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where this IP directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository. 
+
+How to use the IP:
+Step 1: Create a Vivado project
+Step 2: Set the Project Settings to point to the IP path
+Step 3: Create a block design
+Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports
+Step 5: Create a HDL wrapper
+Step 6: Add constraints file (.xdc)
+Step 7: Synthesize, implement, and generate the bitstream
+Step 8: Connect the board, download the bitstream, and varify the design

Library/Interface/7-Segments-Display/seg7display_1.0/src/seg7display.v

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+`timescale 1ns / 1ps
+/////////////////////////////////////////////////////////////////
+// Module Name: seg7display
+// Description: 7-segment display module driving either 4 or 8 7-segments module(s) 
+// Input clock is 100 MHz, reset is high-level logic, input x is either 4 or 8 nibbles input
+// Decimal point is turned OFF
+// Segments are refreshed at approximately 50 Hz.
+// MODULES=1 will use 4 modules where as MODULES=2 will use 8 modules
+/////////////////////////////////////////////////////////////////
+//           a
+//          ---
+//        f|    | b
+//         | g  |
+//          ---
+//        e|    | c
+//         |    |
+//          ---
+//           d
+/////////////////////////////////////////////////////////////////
+
+module seg7display#(parameter MODULES=1, 
+        DP_0=1, DP_1=1, DP_2=1, DP_3=1, 
+        DP_4=1, DP_5=1, DP_6=1, DP_7=1)
+(
+    input wire [15:0] x_l,
+    input wire [15:0] x_h=0,
+    input wire clk,
+    input wire reset,
+    output reg [6:0] a_to_g,
+    output wire [3:0] an_l,
+    output wire [3:0] an_h,
+    output reg dp_l,
+    output reg dp_h 
+);
+
+wire [2:0] s;     
+reg [3:0] digit;
+wire [3:0] aen_l;
+wire [3:0] aen_h;
+wire [7:0] aen;
+reg [7:0] an;
+reg [20:0] clkdiv;
+
+wire [3:0] dp_l_i;
+wire [3:0] dp_h_i;
+wire [7:0] dpen;
+
+assign dp_l_i[0] = (DP_0) ? 1'b0 : 1'b1;
+assign dp_l_i[1] = (DP_1) ? 1'b0 : 1'b1;
+assign dp_l_i[2] = (DP_2) ? 1'b0 : 1'b1;
+assign dp_l_i[3] = (DP_3) ? 1'b0 : 1'b1;
+assign dp_h_i[0] = (DP_4) ? 1'b0 : 1'b1;
+assign dp_h_i[1] = (DP_5) ? 1'b0 : 1'b1;
+assign dp_h_i[2] = (DP_6) ? 1'b0 : 1'b1;
+assign dp_h_i[3] = (DP_7) ? 1'b0 : 1'b1;
+assign s = (MODULES==1) ? {1'b0,clkdiv[19:18]} : clkdiv[20:18];
+assign aen_l = 4'b1111; // all turned off initially
+assign aen_h = 4'b1111; // all turned off initially
+assign aen = (MODULES==1) ? {4'b0000,aen_l} : {aen_h,aen_l};
+assign {an_h,an_l}=an;
+
+assign dpen = (MODULES==1) ? {4'b0000,dp_l_i} : {dp_h_i,dp_l_i};
+
+// MUX
+always @(posedge clk)
+    case(s)
+        0:digit = x_l[3:0]; // s is 000 -->0 ;  digit gets assigned 4 bit value assigned to x[3:0]
+        1:digit = x_l[7:4]; // s is 001 -->1 ;  digit gets assigned 4 bit value assigned to x[7:4]
+        2:digit = x_l[11:8]; // s is 010 -->2 ;  digit gets assigned 4 bit value assigned to x[11:8]
+        3:digit = x_l[15:12]; // s is 011 -->3 ;  digit gets assigned 4 bit value assigned to x[15:12]
+        4:digit = x_h[3:0]; // s is 100 -->4 ;  digit gets assigned 4 bit value assigned to x[19:16]
+        5:digit = x_h[7:4]; // s is 101 -->5 ;  digit gets assigned 4 bit value assigned to x[23:20]
+        6:digit = x_h[11:8]; // s is 110 -->6 ;  digit gets assigned 4 bit value assigned to x[27:24]
+        7:digit = x_h[15:12]; // s is 111 -->7 ;  digit gets assigned 4 bit value assigned to x[31:28]
+        default:digit = x_l[3:0];
+    endcase
+
+//decoder or truth-table for 7a_to_g display values
+always @(*)
+
+    case(digit)
+        //////////////gfedcba///////////
+        0:a_to_g = 7'b1000000;   //0000                                                                    
+        1:a_to_g = 7'b1111001;   //0001                                                
+        2:a_to_g = 7'b0100100;   //0010                                                
+        3:a_to_g = 7'b0110000;   //0011                                             
+        4:a_to_g = 7'b0011001;   //0100                                               
+        5:a_to_g = 7'b0010010;   //0101                                               
+        6:a_to_g = 7'b0000010;   //0110
+        7:a_to_g = 7'b1111000;   //0111
+        8:a_to_g = 7'b0000000;   //1000
+        9:a_to_g = 7'b0010000;   //1001
+        'hA:a_to_g = 7'b0001000; //1010
+        'hB:a_to_g = 7'b0000011; //1011
+        'hC:a_to_g = 7'b1000110; //1100
+        'hD:a_to_g = 7'b0100001; //1101
+        'hE:a_to_g = 7'b0000110; //1110
+        'hF:a_to_g = 7'b0001110; //1111
+        default: a_to_g = 7'b0000000; // all segments ON
+    endcase
+
+always @(*)begin
+    if(MODULES==1)
+    begin
+        an=8'b00001111;
+        if(aen_l[s] == 1)
+            an[s] = 0;
+    end
+    else
+    begin
+        an=8'b11111111;
+        if(aen[s] == 1)
+            an[s] = 0;
+    end       
+end
+
+always @(*)begin
+    if(MODULES==1)
+    begin
+        if(aen_l[s] == 1)
+            dp_l = dpen[s];
+    end
+    else
+    begin
+        if(aen[s] == 1) begin
+            if(s<4) 
+                dp_l = dpen[s];
+            else
+                dp_h = dpen[s];
+        end
+    end       
+end
+
+//clkdiv
+always @(posedge clk) begin
+    if ( reset == 1)
+        clkdiv <= 0;
+    else
+        clkdiv <= clkdiv+1;
+end
+
+endmodule
+

Library/Interface/7-Segments-Display/seg7display_1.0/xgui/seg7display_v1_0.tcl

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+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "MODULES" -parent ${Page_0}
+  ipgui::add_static_text $IPINST -name "Number of Modules" -parent ${Page_0} -text {Selecting 1 will provide one 16-bit input and one 4-bit anodes output ports. 
+Selecting 2 will provide two 16-bit input and two 4-bit anodes output ports.
+The IP expects 100 MHz input clock.
+
+Please select Decimal Points display in the other two tabs}
+
+  #Adding Page
+  set Module_1_Related_Decimal_Points [ipgui::add_page $IPINST -name "Module 1 Related Decimal Points"]
+  ipgui::add_param $IPINST -name "DP_0" -parent ${Module_1_Related_Decimal_Points} -widget comboBox
+  ipgui::add_param $IPINST -name "DP_1" -parent ${Module_1_Related_Decimal_Points} -widget comboBox
+  ipgui::add_param $IPINST -name "DP_2" -parent ${Module_1_Related_Decimal_Points} -widget comboBox
+  ipgui::add_param $IPINST -name "DP_3" -parent ${Module_1_Related_Decimal_Points} -widget comboBox
+
+  #Adding Page
+  set Module_2_Related_Decimal_Points [ipgui::add_page $IPINST -name "Module 2 Related Decimal Points"]
+  ipgui::add_param $IPINST -name "DP_4" -parent ${Module_2_Related_Decimal_Points} -widget comboBox
+  ipgui::add_param $IPINST -name "DP_5" -parent ${Module_2_Related_Decimal_Points} -widget comboBox
+  ipgui::add_param $IPINST -name "DP_6" -parent ${Module_2_Related_Decimal_Points} -widget comboBox
+  ipgui::add_param $IPINST -name "DP_7" -parent ${Module_2_Related_Decimal_Points} -widget comboBox
+
+
+}
+
+proc update_PARAM_VALUE.DP_0 { PARAM_VALUE.DP_0 } {
+	# Procedure called to update DP_0 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DP_0 { PARAM_VALUE.DP_0 } {
+	# Procedure called to validate DP_0
+	return true
+}
+
+proc update_PARAM_VALUE.DP_1 { PARAM_VALUE.DP_1 } {
+	# Procedure called to update DP_1 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DP_1 { PARAM_VALUE.DP_1 } {
+	# Procedure called to validate DP_1
+	return true
+}
+
+proc update_PARAM_VALUE.DP_2 { PARAM_VALUE.DP_2 } {
+	# Procedure called to update DP_2 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DP_2 { PARAM_VALUE.DP_2 } {
+	# Procedure called to validate DP_2
+	return true
+}
+
+proc update_PARAM_VALUE.DP_3 { PARAM_VALUE.DP_3 } {
+	# Procedure called to update DP_3 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DP_3 { PARAM_VALUE.DP_3 } {
+	# Procedure called to validate DP_3
+	return true
+}
+
+proc update_PARAM_VALUE.DP_4 { PARAM_VALUE.DP_4 } {
+	# Procedure called to update DP_4 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DP_4 { PARAM_VALUE.DP_4 } {
+	# Procedure called to validate DP_4
+	return true
+}
+
+proc update_PARAM_VALUE.DP_5 { PARAM_VALUE.DP_5 } {
+	# Procedure called to update DP_5 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DP_5 { PARAM_VALUE.DP_5 } {
+	# Procedure called to validate DP_5
+	return true
+}
+
+proc update_PARAM_VALUE.DP_6 { PARAM_VALUE.DP_6 } {
+	# Procedure called to update DP_6 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DP_6 { PARAM_VALUE.DP_6 } {
+	# Procedure called to validate DP_6
+	return true
+}
+
+proc update_PARAM_VALUE.DP_7 { PARAM_VALUE.DP_7 } {
+	# Procedure called to update DP_7 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DP_7 { PARAM_VALUE.DP_7 } {
+	# Procedure called to validate DP_7
+	return true
+}
+
+proc update_PARAM_VALUE.MODULES { PARAM_VALUE.MODULES } {
+	# Procedure called to update MODULES when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.MODULES { PARAM_VALUE.MODULES } {
+	# Procedure called to validate MODULES
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.MODULES { MODELPARAM_VALUE.MODULES PARAM_VALUE.MODULES } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.MODULES}] ${MODELPARAM_VALUE.MODULES}
+}
+
+proc update_MODELPARAM_VALUE.DP_0 { MODELPARAM_VALUE.DP_0 PARAM_VALUE.DP_0 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DP_0}] ${MODELPARAM_VALUE.DP_0}
+}
+
+proc update_MODELPARAM_VALUE.DP_1 { MODELPARAM_VALUE.DP_1 PARAM_VALUE.DP_1 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DP_1}] ${MODELPARAM_VALUE.DP_1}
+}
+
+proc update_MODELPARAM_VALUE.DP_2 { MODELPARAM_VALUE.DP_2 PARAM_VALUE.DP_2 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DP_2}] ${MODELPARAM_VALUE.DP_2}
+}
+
+proc update_MODELPARAM_VALUE.DP_3 { MODELPARAM_VALUE.DP_3 PARAM_VALUE.DP_3 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DP_3}] ${MODELPARAM_VALUE.DP_3}
+}
+
+proc update_MODELPARAM_VALUE.DP_4 { MODELPARAM_VALUE.DP_4 PARAM_VALUE.DP_4 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DP_4}] ${MODELPARAM_VALUE.DP_4}
+}
+
+proc update_MODELPARAM_VALUE.DP_5 { MODELPARAM_VALUE.DP_5 PARAM_VALUE.DP_5 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DP_5}] ${MODELPARAM_VALUE.DP_5}
+}
+
+proc update_MODELPARAM_VALUE.DP_6 { MODELPARAM_VALUE.DP_6 PARAM_VALUE.DP_6 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DP_6}] ${MODELPARAM_VALUE.DP_6}
+}
+
+proc update_MODELPARAM_VALUE.DP_7 { MODELPARAM_VALUE.DP_7 PARAM_VALUE.DP_7 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DP_7}] ${MODELPARAM_VALUE.DP_7}
+}
+